1. Field of the Invention
The present invention relates to a field-effect transistor having an MIS (Metal-Insulator-Semiconductor) structure (hereinafter referred to as xe2x80x9cMIS transistorxe2x80x9d), and particularly to an MIS transistor having an LDD (Lightly Doped Drain) structure.
2. Description of the Background Art
FIGS. 40 to 44 are sectional views showing a conventional method for manufacturing an MIS transistor in the order of process steps. Ion implantation for well, channel, etc. (not shown) is applied to the area element-isolated by the silicon oxide 2 formed on the main surface of the silicon substrate 1 (hereinafter referred to as xe2x80x9cactive regionxe2x80x9d) and then a gate insulating film 4 and polysilicon 3 are formed on the silicon substrate 1 in this order. Next impurity ions 6 are implanted into the active region using as a mask the gate insulating film 4 and the polysilicon 3 shaped by lithography technique in the same shape as seen in a plane view. This implantation forms extensions 5 in the LDD structure, which have lower impurity concentration and are relatively thin and located close to the gate electrode, thus providing the structure shown in FIG. 40. The polysilicon 3, which functions as the gate electrode, may be referred to as gate electrode 3 hereinafter.
Next silicon nitride film and silicon oxide film are deposited in this order on the upper surface of the structure shown in FIG. 40. Then the films are etched back to form sidewalls of the silicon oxide films 7 and the silicon nitride films 8 on the sides of the gate electrode 3 (FIG. 41).
Next impurity ions 10 are implanted to form a pair of source/drain 9 in the LDD structure, which have higher impurity concentration and are relatively thick and separated away from the gate electrode 3 (FIG. 42). A thermal process is then applied to electrically activate the impurity introduced in the source/drain 9 by the ion implantation (hereinafter referred to as xe2x80x9cdrive of source/drainxe2x80x9d), thus providing the structure shown in FIG. 43. RTA (Rapid Thermal Annealing) at 900 to 1200xc2x0 C. for 1 to 60 sec is usually adopted for the drive of the source/drain.
Next so-called salicidation (salicide: self-aligned silicide) process is applied to the structure shown in FIG. 43 to form cobalt silicide 13 and the structure shown in FIG. 44 is thus obtained. The MIS transistor thus obtained undergoes processes for forming interlayer film, interconnections, etc. as required.
What is important for scaling down of the MIS transistor thus manufactured is control of the shape of junctions at the extensions 5. First, forming shallow junctions at the extensions 5 can reduce the effect that the depletion layer extending from the drain part of the source/drain 9 exerts on the source part of the source/drain 9 (short-channel effect).
When the extensions 5 are formed as a pair of an equal depth, the distance We between the pair of extensions 5 (FIG. 44) corresponds to the effective gate length and the characteristics of the MIS transistor are approximately determined by the distance We. Accordingly, even when the physical gate length, or the length Wg of the gate electrode 3 (FIG. 44) is designed equal, the characteristics of the MIS transistor differ depending on the distance We between the extensions 5. The length Wg of the gate electrode 3 is adopted when designing an MIS transistor. Accordingly, in order to achieve agreement of the MIS transistor operation between design and measurement, it is desired that the distance We between the pair of extensions 5 is approximately equal to the length Wg of the gate electrode 3.
In general, the solid solubility of an impurity becomes larger as the temperature becomes higher. Lower temperature in thermal process can only activate impurity concentration determined by the solid solubility. Therefore activating higher impurity concentration requires thermal process at higher temperature. Since the impurity concentration in the extensions 5 is usually lower than that in the source/drain 9, the activation of the extensions 5 does not require such high temperature as the drive of the source/drain 9 does.
In the above-described conventional method for manufacturing MOSFET, however, the drive of the source/drain 9 is performed after the implantation of the impurity ions 6 for the extensions 5 (FIG. 42). Accordingly, since the drive of the source/drain 9 is applied to the extensions 5 as excessive heat, the drive of the source/drain 9 causes the impurity in the extensions 5 to excessively diffuse. FIG. 45 is a graph showing the diffusion in the extensions 5 caused by the drive of the source/drain 9. The thermal processing temperature increases in the order of the curves 81, 82 and 83. This graph shows a tendency that the impurity diffuses deeper from the surface as the thermal processing temperature rises. This tendency is also observed when the thermal processing time is lengthened. That is to say, referring to FIG. 43, the extensions 5 diffuse in the depth direction vertical to the main surface of the silicon substrate 1 and its thickness De becomes larger.
The drive of the source/drain 9 also causes the opposing ends of the pair of extensions 5 to expand in the direction parallel to the main surface of the silicon substrate 1, which increases the amount of overlap, Wo, of the gate electrode 3 and the extensions 5 (FIG. 43). This increases the difference between the effective gate length and the physical gate, which is a disadvantageous factor in design and manufacture of MIS transistors having fine gate length.
Furthermore, the thermal process for obtaining the salicide structure, too, is performed after the implantation of the impurity ions 6. This order of manufacturing steps serves as a factor which reduces the distance We between the pair of extensions 5 as well.
Techniques for applying ion implantation through sidewalls are disclosed in Japanese Patent Application Laid-Open No.6-333943 (1994), Japanese Patent Applicatin Laid-Open No.7-142726 (1995), and Japanese Patent Application Laid-Open No.10-200097 (1998), for example.
According to a first aspect of the present invention, a semiconductor device manufacturing method comprises the steps of: (a) forming a gate insulating film on a main surface of a semiconductor substrate and a gate electrode on the semiconductor substrate with the gate insulating film interposed therebetween; (b) forming a first sidewall covering a side of the gate electrode and the gate insulating film and the main surface in a first region which extends for a first width from the side outward from the gate electrode; (c) introducing a first impurity into the main surface by using the first sidewall and the gate electrode as a mask to form a first impurity region; (d) applying a thermal process to the structure obtained in the step (c) to electrically activate the first impurity; (e) forming a second sidewall by reducing the thickness of the first sidewall to a thickness smaller than that of the gate electrode, leaving part of the first sidewall which covers the side in a second region extending for a second width from the side outward from the gate electrode, the second width being smaller than the first width; and (f) after the step (d), introducing a second impurity through the second sidewall by using the gate electrode as a mask to form a second impurity region having an impurity concentration lower than that of the first impurity region.
According to the first aspect of the invention, the first sidewall prevents the first impurity from being introduced into the main surface in the first region. However, since the second sidewall is thinner than the first sidewall except in the second region, the second impurity is introduced into the main surface except in the second region. The impurity concentration in the second impurity region is lower than that in the first impurity region, which realizes a so-called LDD structure. Since the step (d) precedes the step (f), the step (f) is not affected by the thermal process in the step (d). Accordingly, the dimensions of the second impurity region can accurately be controlled independently of control of the shape of the first impurity region. Furthermore, the second sidewall prevents the second impurity from being introduced into the main surface in the second region. This alleviates penetration of the second impurity region under the gate electrode.
Preferably, according to a second aspect of the invention, in the semiconductor device manufacturing method, the step (b) comprises the steps of; (b-1) applying thermal nitridation to the side and the main surface to form a nitride film, and (b-2) depositing on the nitride film a material which can be etched more easily than the nitride film.
According to the second aspect of the invention, the step (e) can easily be achieved by etching.
Preferably, according to a third aspect of the present invention, in the semiconductor device manufacturing method, the semiconductor substrate is a silicon substrate and a silicon oxide film is deposited on the nitride film in the step (b-2).
Preferably, according to a fourth aspect of the present invention, in the semiconductor device manufacturing method, the step (b) further comprises a step of (b-3) etching back the nitride film and the silicon oxide film to form the first sidewall and the nitride film etched back in the step (b-3) functions as the second sidewall.
According to the fourth aspect of the invention, the effect of the first aspect is not hindered because the thermal process required for formation of the second sidewall is performed before the step (f).
Preferably, according to a fifth aspect of the invention, the semiconductor device manufacturing method further comprises a step of (g) thickening the semiconductor substrate on the main surface separated from the side of the gate electrode by the first width or more.
Preferably, according to a sixth aspect of the present invention, in the semiconductor device manufacturing method, the step (g) is performed between the step (b) and the step (f).
According to the sixth aspect of the invention, it is possible to manufacture a semiconductor device with raised source/drain structure. Even if the process of thickening the semiconductor substrate needs high-temperature processing, the effect of the first aspect is not hindered because the step (g) is performed before the step (f).
Preferably, according to a seventh aspect of the present invention, in the semiconductor device manufacturing method, the step (g) is performed after the step (c).
Preferably, according to an eighth aspect of the present invention, in the semiconductor device manufacturing method, the step (g) is performed after the step (d).
Preferably, according to a ninth aspect of the present invention, in the semiconductor device manufacturing method, the step (g) is performed after the step (e).
Preferably, according to a tenth aspect of the present invention, in the semiconductor device manufacturing method, epitaxial growth of a semiconductor is performed in the step (g).
Preferably, according to an eleventh aspect of the present invention, in the semiconductor device manufacturing method, in the step (a), top surface of the gate electrode is formed with an insulator which hinders the epitaxial growth of the semiconductor.
According to the eleventh aspect of the invention, the epitaxial growth performed in the step (g) does not cause epitaxial layer to grow on the upper surface of the gate electrode. Also, even if the gate electrode functions as a mask in the introduction of the first impurity in the step (c), the first impurity is introduced into the insulator. Accordingly, the impurity concentration in the gate electrode is not changed and the threshold of the semiconductor device is not affected.
Preferably, according to a twelfth aspect of the present invention, in the semiconductor device manufacturing method, the semiconductor obtained by the epitaxial growth comprises silicon.
Preferably, according to a thirteenth aspect of the present invention, in the semiconductor device manufacturing method, the semiconductor obtained by the epitaxial growth is amorphous.
Preferably, according to a fourteenth aspect of the present invention, in the semiconductor device manufacturing method, the semiconductor obtained by the epitaxial growth further comprises germanium.
Preferably, according to a fifteenth aspect of the invention, the semiconductor device manufacturing method further comprises a step of (g) applying salicidation process to the semiconductor substrate in the main surface separated from the side of the gate electrode by the first width or more.
Preferably, according to a sixteenth aspect of the present invention, in the semiconductor device manufacturing method, the step (g) is performed before the step (f).
According to the sixteenth aspect of the invention, the step (g) is performed prior to the step (f) of forming the extension region, so that the salicidation reaction can occur in the source/drain without hindering the effect of the first aspect.
Preferably, according to a seventeenth aspect of the present invention, in the semiconductor device manufacturing method, in the step (f), ions of the second impurity are implanted obliquely with respect to the normal direction of the main surface.
According to the seventeenth aspect of the invention, the position of the end of the second impurity region can be controlled not only by the second width but also by the angle of ion implantation. This is particularly suitable for applications in which the second sidewall is thick and the impurity in the second impurity region is not activated.
Preferably, according to an eighteenth aspect of the present invention, in the semiconductor device manufacturing method, the second sidewall is composed of stacked layers of a silicon oxide film in contact with the semiconductor substrate and a silicon nitride film provided on the semiconductor substrate with the silicon oxide film interposed therebetween.
The present invention has been made in view of the above-described technical background, and an object of the invention is to provide a method for manufacturing an MIS transistor which can prevent unwanted diffusion of extensions caused by the drive of source/drain and thermal process for obtaining a salicide structure so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain optimum structures for them.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
FIGS. 1 to 8 are sectional views showing, in the order of process steps, an MIS transistor manufacturing method according to a first preferred embodiment of this invention.
FIGS. 9 to 16 are sectional views showing, in the order of process steps, an MIS transistor manufacturing method according to a second preferred embodiment of this invention.
FIGS. 17 to 22 are sectional views showing, in the order of process steps, an MIS transistor manufacturing method according to a third preferred embodiment of this invention.
FIGS. 23 to 25 are sectional views showing, in the order of process steps, an MIS transistor manufacturing method according to a fourth preferred embodiment of this invention, which is based on the first preferred embodiment.
FIGS. 26 to 28 are sectional views showing, in the order of process steps, the MIS transistor manufacturing method according to the fourth preferred embodiment of this invention, which is based on the second preferred embodiment.
FIGS. 29 to 31 are sectional views showing, in the order of process steps, the MIS transistor manufacturing method according to the fourth preferred embodiment of this invention, which is based on the third preferred embodiment.
FIGS. 32 to 34 are sectional views showing an MIS transistor manufacturing method according to a fifth preferred embodiment of this invention, which is based on the second preferred embodiment.
FIGS. 35 to 37 are sectional views showing the MIS transistor manufacturing method according to the fifth preferred embodiment of this invention, which is based on the third preferred embodiment.
FIGS. 38 and 39 are sectional views showing an MIS transistor manufacturing method according to a sixth preferred embodiment of this invention, which is based on the first preferred embodiment.
FIGS. 40 to 44 are sectional views showing a conventional art in the order of process steps.
FIG. 45 is a graph showing diffusion of the extensions caused by drive of the source/drain.